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DS3105
110
Table 10-3. CMOS/TTL Pins
(VDD = 1.8V ±10%; VDDIO = 3.3V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2.0
5.5
V
Input Low Voltage
VIL
-0.3
+0.8
V
Input Leakage
IIL
(Note 1)
-10
+10
A
Input Leakage, Pins with Internal
Pullup Resistor (50k
typ)
IILPU
(Note 1)
-100
+10
A
Input Leakage, Pins with Internal
Pulldown Resistor (50k
typ)
IILPD
(Note 1)
-10
+100
A
Output Leakage (when High-Z)
ILO
(Note 1)
-10
+10
A
Output High Voltage (IO = -4.0mA)
VOH
2.4
VDDIO
V
Output Low Voltage (IO = +4.0mA)
VOL
0
0.4
V
Note 1:
0V < VIN < VDDIO for all other digital inputs.
Table 10-4. LVDS/LVPECL Input Pins
(VDD = 1.8V ±10%; VDDIO = 3.3V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Voltage Tolerance
VTOL
(Note 1)
0
VDDIO
V
Input Voltage Range
VIN
VID = 100mV
0
2.4
V
Input Differential Voltage
VID
0.1
1.4
V
Input Differential Logic Threshold
VIDTH
-100
+100
mV
Note 1:
The device can tolerate this range of voltages w.r.t. VSS on its ICxPOS and ICxNEG pins without being damaged. Proper
operation of the differential input circuitry is only guaranteed when the other specifications in this table are met.
Table 10-5. LVDS Output Pins
(VDD = 1.8V ±10%; VDDIO = 3.3V ±5%, TA = -40°C to +85°C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output High Voltage
VOHLVDS
(Note 1)
1.6
V
Output Low Voltage
VOLLVDS
(Note 1)
0.9
V
Differential Output Voltage
VODLVDS
247
350
454
mV
Output Offset (Common Mode) Voltage
VOSLVDS
25
°C (Note 1)
1.125
1.25
1.375
V
Difference in Magnitude of Output
Differential Voltage for Complementary
States
VDOSLVDS
25
mV
Note 1:
With 100
load across the differential outputs.
Note 2:
The differential outputs can easily be interfaced to LVDS, LVPECL, and CML inputs on neighboring ICs using a few external
passive components. See App Note HFAN-1.0 for details.
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